2024/7/30　次世代半導体・センサ科学研究所 第2回 特別講演会

　

Associate Professor Iizuka’s research group has achieved several significant results in phase-locked loop (PLL) technology, which enables extremely low-noise signal generation by utilizing multiple feedback structures and eliminating the need for complex correction.

In this seminar, Associate Professor Tetsuya Iizuka will introduce recent examples of research activities related to these phase-locked loop technologies. He will also discuss examples of undergraduate education related to Agile-X, an initiative of the University of Tokyo’s X-nics Project.

 

Date and Time: Tuesday, July 30, 2024, from 3:00 p.m.
Venue: A2 – Room 201
Registration: Not required
Admission: Free

Supported by:
Green-niX Research and Human Resource Development Center

 

Program

“Phase-Locked Loop Technology Using a Harmonic Mixer in the Feedback Path and Recent VDEC Activities”

Tetsuya Iizuka
Associate Professor, Center for System Design, School of Engineering, The University of Tokyo

 

 

Contact Information

Institute for Research on Next-generation Semiconductor and Sensing Science (IRES²)
Toyohashi University of Technology

Tel/Fax: +81-532-44-6974
Email: office ]at[ eiiris.tut.ac.jp